1. Field of the Invention
The present invention relates to the field of integrated circuit memories, more specifically, the present invention relates to a method and to an apparatus for read measurement of a plurality of resistive memory cells having a plurality of programmable levels.
2. Description of Related Art
A prominent example for resistive memory cells having a plurality of programmable levels is Resistive Random Access Memory (RRAM), particular Phase Change Memory (PCM). PCM is a non-volatile solid-state memory technology that exploits the reversible, thermally-assisted switching of specific chalcogenides between certain states of different electrical conductivity.
PCM is a promising and advanced emerging non-volatile memory technology mainly due to its excellent features including low latency, high endurance, long retention and high scalability. PCM can be considered a prime candidate for Flash replacement, embedded/hybrid memory and storage-class memory. Key requirements for competitiveness of PCM technology can be multi-level cell functionality, in particular for low cost per bit, and high-speed read/write operations, in particular for high bandwidth. Multilevel functionality, i.e. multiple bits per PCM cell, can be a way to increase storage capacity and thereby to reduce cost.
Multi-level PCM is based on storing multiple resistance levels between a lowest (SET) and a highest (RESET) resistance value. Multiple resistance levels or levels correspond to partial-amorphous and partial-crystalline phase distributions of the PCM cell. Phase transformation, i.e. memory programming, can be enabled by Joule heating. In this regard, Joule heating can be controlled by a programming current or voltage pulse. Storing multiple resistance levels in a PCM cell is a challenging task.
In Wong, H.-S Philip et al., “Recent Progress of Phase Change Memory and Resisitve Switching Random Access Memory”, ICSICT, 2010, Proc. IEEE, it is described that multi-level cell (MLC) programming is the most efficient way to increase the storage capacity of PCM. In order to achieve MLC programming, an iterative algorithm can be used, which adapts the programming current to the characteristics of each cell in every cycle so that the cell is programmed to the desired cell-state with minimum write latency (PAPANDREOU, N. et al., “Enabling Technologies for Multilevel Phase-Change Memory”, European Phase Change and Ovonics Symposium, 2011).
When reading MLC data from a memory array including a plurality of memory cells, the read-back signals form Gaussian-like distributions corresponding to the different levels. This is mainly due to noise during the read process, a distribution of programmed cell-states for each level within each target bin during the write process and a non-uniform drift of the difference resistance levels (POZIDIS, H. et al., “A Framework for Reliability Assessment in Multilevel Phase-Change Memory”, Memory Workshop (IMW), pages 1-4, May 2012, 2012 4th IEEE International). Further, the actual level statistics are data-dependent and typically change over time. As a result, an estimation of the first and second-order statistics is essential for reliable level detection (European Patent Application No. 11183336.4). The accuracy of the estimation depends heavily on the number of available data. In main memory applications and hybrid memory applications, the number of data that is collected during memory access can be limited.
Accordingly, it is an aspect of the present invention to improve the read measurement of a plurality of resistive memory cells.